1. Field of the Invention
This invention relates generally to electrically programmable, non-volatile semiconductor memory devices and manufacturing method thereof, and more particularly to improved flash-type non-volatile memory devices and manufacturing method thereof.
2. Description of the Background Art
An electrically erasable programmable read only memory (hereinafter referred to as an EEPROM) is known in the art as a type of the semiconductor memory device in which the stored program can be electrically altered and erased. In order to have a brief background idea of the invention, reference is first made to FIG. 1 which shows in block diagram an overall arrangement of a typical prior-art EEPROM.
As shown, the EEPROM includes a memory array 50 formed of a plurality of EEPROM cells, a row address buffer 51 for receiving externally applied row address signal and a column address buffer 52 which receives externally applied column address signals. The EEPROM also includes a row decoder 53 and a column decoder 54. The row decoder 53 decodes the address output from the row address buffer 51 and activates a word line coupled to a particular memory cell to be selected in the memory array, while the column decoder 54 decodes the address output from the column address buffer 52 to activate a Y gate 55 to connect a bit line coupled to the particular memory cell to I/O line. A sense amplifier 56 senses via Y gate 55 a data signal stored in the memory cell which has been selected by the row and column decoders. The sensed signal is, after amplified in the sense amplifier 56, fed out through an output buffer 57. Included also in the EEPROM is an input buffer 58 for providing control signals to various circuits associated with the memory array.
In recent years, it has been proposed a new type of an EEPROM where tunneling current through a thin oxide layer on a semiconductor substrate is used to control the flow of charging electrons into or out of a charge storing floating gate provided on the semiconductor substrate. One such EEPROM is disclosed in Japanese Patent Publication No. 41,431/1987.
Referring now to FIGS. 2A and 2B, there is illustrated a conventional 2-transistor type memory cell for an EEPROM. The 2-transistor memory cell includes a floating gate transistor TR1 and a select gate transistor TR2, both formed on the major surface of a semiconductor substrate 1. The floating gate transistor TR1 comprises a drain region 62, a source region 63, a tunneling oxide layer 64, a floating gate 65 and a control gate 66. Of these components parts, the drain region 62 and source region 63 are provided in the major surface of the semiconductor substrate 1. The tunneling oxide layer 64 is a thin oxide layer deposited over a predetermined area of the drain region 62. The floating gate 65 is made of a polysilicon layer formed over the substrate 1 at least partially to overlap or overlie the tunnel oxide layer 64, and separated therefrom by an intervening insulating layer. On the other hand, the control gate 66 is formed to overlie the floating gate 65 and to be separated by an interposed insulating layer. Overlapped control and floating gates 66 and 65 produce a capacitor with the interposed insulating layer serving as a dielectric material. The floating gate 65 and the drain region 62 form another capacitor with the tunnel oxide layer sandwiched by them serving as dielectric material. The floating gate 65 and the semiconductor substrate 1 also form a capacitor at the area other than the area in contact with the tunneling oxide layer 64. As is known in the art, the floating gate 65 is for storing electrical charge. Depending on the potential applied between the control gate 66 and the drain region 62, electrical charge is injected from the drain region 62 through the tunnel oxide layer 64 into the floating gate 65, or the charge is removed out of the floating gate 65 through the tunneling oxide layer 64 to the drain region 62.
The select transistor TR2 comprises a source region 62 (which also serves as the drain region of the floating gate transistor TR1) and a drain region 67 both provided on the major surface of the semiconductor substrate 1, and a gate electrode 68 which serves as a word line. A bit line 69 is connected to the drain region 67 through a contact hole.
The select transistor TR2 turns on or off in response to the signal supplied through the word line 68 thereby to read out the data stored in the floating gate transistor 1 through the bit line 69.
As stated, the memory cell for the conventional EEPROM is made up of two transistors: a select transistor and a floating gate memory transistor. The select transistor is provided for programming in terms of a byte. However, the provision of the additional select transistor is disadvantageous in that is increases the overall area of each memory cell, and thus of the chip area in a high density semiconductor memory device. In order to overcome this problem, a new type of EEPROM called a flash EEPROM which is a one-transistor memory capable of electrically erasing all the data stored therein simultaneously.
In FIG. 3A, there is illustrated an equivalent circuit for one memory cell in the conventional flash EEPROM, and FIG. 3B shows an equivalent circuit of a four-bit memory configuration using the one-transistor memory cell of FIG. 3A. The memory cell comprises a single floating gate transistor. The floating transistor has a control gate 2 to be connected to word lines W1 and W2, and a source region 7 to be coupled to source lines S1 and S2. The floating gate transistor also has a drain region 8 to be linked to bit lines B1 and B2, and a floating gate 3 provided on the side of the control gate 2 adjacent or near the drain region 8. The floating gate 3 is for storing electrical charge. Depending on the voltage applied between the control gate 2 and the drain region 8, electrical charge is injected into the floating gate 3 from the channel region into the substrate 1, or it is removed from the floating gate 3 to the channel region thereby to write data into the floating gate 3 or to erase the data stored in the floating gate 3. In reading out the data stored in the floating gate transistor, the transistor is turned on/off in response to the signal applied by the word lines W1 and W2 to transfer the stored data out onto the bit lines B1 and B2 coupled to the drain region 8. The writing and reading of the data onto the floating gate is performed by applying a desired voltage to the necessary bit lines B1 and B2 and the word lines W1 and W2. For the erasure of the data, an erasing voltage is applied to all the bit lines B1 and B2, removing all the data stored in all the memory cells simultaneously.
Referring to FIGS. 4-7, there is shown a conventional one-transistor type flash EEPROM as disclosed, for example, in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5 (1987, pp. 676-683).
As shown, on a semiconductor substrate 1 of monocrystalline silicon such as a p-type silicon substrate, an n-type source regions 7 and n-type drain regions 8 are created spaced apart from one another. Control gates 2 and floating gates 3 are provide so that channel regions are formed between the control gate 2 and the floating gate 3. The control gate 2 is formed on the substrate 1 and is separated therefrom by a thick gate oxide layer 4. Likewise, the floating gate 3 is formed on the substrate 1 and is separated therefrom by a thin gate oxide layer (FIG. 7). One end portion of the control gate 2 which also serves as the word line overlies the floating gate 3 with a thin insulating layer 6 interposed between them. The other end portion of the control gate 2 extends partially over the thick gate oxide layer 4. The control gate 2 and the underlying floating gate 3 are formed using mask and etched technique so that they overlapped each other over a predetermined plane area. The source region 7 and the drain region 8 placed on the opposite sides of the control and floating gates 2 and 3 are formed in a self-alignment manner by doping impurities into the substrate using the control gate and the floating gate as the masks.
The source region 7 is disposed in the substrate on the side of the control gate 2 which extends over the gate oxide layer 4, while the drain region 8 is positioned on the side of the control gate 2 overlying the floating gate 3. In this manner, the control gate 2 partially overlaps the source region 7 with the thick gate oxide layer 4 disposed between them, and the floating gate 3 partially overlaps the drain region 8 with the thin gate oxide layer 5 placed between them. There is deposited over the control gate 2 an insulating layer 9, through which a contact hole 10 is made to extend to the drain region 8. An aluminum interconnection 11 serving also as the bit line is deposited over the insulating layer 9 and electrically communicated to the drain region 8 via the contact hole 10.
Provided around the memory cell thus formed is a thick field oxide layer 12 for device isolation. The control gate 2 and the floating gate 3 partially overlies the thick field oxide layer 12. Created in the substrate directly below the field oxide layer 12 is a channel stopper region 13 of p-type impurity for the prevention of leakage current.
In the conventional EEPROM structure, the control gate 2 and the floating gate 3 are formed by means of mask and etch technique. Specifically, the one end portion of the control gate 2 overlies the floating gate 3 over a predetermined area with the thin insulating layer 6 disposed between them to provide a prescribed coupling capacitance. The other end portion of the control gate 2 extend adjacent to the source region 7 with the gate oxide layer positioned between them. In short, the control gate 2 must have a portion thereof overlapped the underlying floating gate 3. Also, it has to extend adjacent to the source region. The design requirements inevitably increases the memory cell area, thereby preventing further miniaturization of the memory cell.
As previously stated, the control gate 2 and the floating gate 3 are formed to partially overlap over a predetermined area using mask and etch technique. Any mask misalignment causes a displacement of not only the channel region created in the substrate below the control gate but also the overlapped area between the control gate and the floating gate. Consequently, memory cell in the EEPROM may have channel regions of varying length and different cell currents. A greater channel length in a memory cell increases the cell resistance and reduces the cell current. Moreover, if the coupling capacitance between the control gate and the floating gate differs from memory cell to memory cell, unstable data storage states in the memory cells and differing read-out currents would result.